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1 motorola tmos power mosfet transistor device data
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" "! nchannel enhancementmode silicon gate the d 2 pak package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower r ds(on) capabilities. this high voltage mosfet uses an advanced termination scheme to provide enhanced voltageblocking capability without degrading perfor- mance over time. in addition, this advanced tmos efet is designed to withstand high energy in the avalanche and commuta- tion modes. the new energy efficient design also offers a draintosource diode with a fast recovery time. designed for high voltage, high speed switching applications in power supplies, converters and pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. ? robust high voltage termination ? avalanche energy specified ? sourcetodrain diode recovery time comparable to a discrete fast recovery diode ? diode is characterized for use in bridge circuits ? i dss and v ds(on) specified at elevated temperature ? short heatsink tab manufactured e not sheared ? specially designed leadframe for maximum power dissipation ? available in 24 mm 13inch/800 unit tape & reel, add t4 suffix to part number maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drainsource voltage v dss 800 vdc draingate voltage (r gs = 1.0 m w ) v dgr 800 vdc gatesource voltage e continuous gatesource voltage e nonrepetitive (t p 10 ms) v gs v gsm 20 40 vdc vpk drain current e continuous drain current e continuous @ 100 c drain current e single pulse (t p 10 m s) i d i d i dm 4.0 2.9 12 adc apk total power dissipation derate above 25 c total power dissipation @ t a = 25 c, when mounted with the minimum recommended pad size p d 125 1.0 2.5 watts w/ c watts operating and storage temperature range t j , t stg 55 to 150 c single pulse draintosource avalanche energy e starting t j = 25 c (v dd = 100 vdc, v gs = 10 vdc, i l = 8.0 apk, l = 10 mh, r g = 25 w ) e as 320 mj thermal resistance e junction to case thermal resistance e junction to ambient thermal resistance e junction to ambient, when mounted with the minimum recommended pad size r q jc r q ja r q ja 1.0 62.5 50 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c designer's data for aworst caseo conditions e the designer's data sheet permits the design of most circuits entirely from the information presented. soa limit curves e representing boundaries on device characteristics e are given to facilitate aworst caseo design. efet and designer's are trademarks of motorola, inc. tmos is a registered trademark of motorola, inc. thermal clad is a trademark of the bergquist company. preferred devices are motorola recommended choices for future use and best overall value. rev 4 order this document by mtb4n80e/d semiconductor technical data tmos power fet 4.0 amperes 800 volts r ds(on) = 3.0 ohm motorola preferred device case 418b02, style 2 d 2 pak d s g ? ? motorola, inc. 1996
2 motorola tmos power mosfet transistor device data electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drainsource breakdown voltage (v gs = 0 vdc, i d = 250 m adc) temperature coefficient (positive) v (br)dss 800 e e 1.02 e e vdc mv/ c zero gate voltage drain current (v ds = 800 vdc, v gs = 0 vdc) (v ds = 800 vdc, v gs = 0 vdc, t j = 125 c) i dss e e e e 10 100 m adc gatebody leakage current (v gs = 20 vdc, v ds = 0) i gss e e 100 nadc on characteristics (1) gate threshold voltage (v ds = v gs , i d = 250 m adc) temperature coefficient (negative) v gs(th) 2.0 e 3.0 7.0 4.0 e vdc mv/ c static drainsource onresistance (v gs = 10 vdc, i d = 2.0 adc) r ds(on) e 1.95 3.0 ohm drainsource onvoltage (v gs = 10 vdc) (i d = 4.0 adc) (i d = 2.0 adc, t j = 125 c) v ds(on) e e 8.24 e 12 10 vdc forward transconductance (v ds = 15 vdc, i d = 2.0 adc) g fs 2.0 4.3 e mhos dynamic characteristics input capacitance (v 25 vdc v 0 vdc c iss e 1320 2030 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss e 187 400 reverse transfer capacitance f = 1 . 0 mhz) c rss e 72 160 switching characteristics (2) turnon delay time (v 400 vd i 4 0 ad t d(on) e 13 30 ns rise time (v dd = 400 vdc, i d = 4.0 adc, v gs =10vdc t r e 36 90 turnoff delay time v gs = 10 vd c, r g = 9.1 w ) t d(off) e 40 80 fall time g ) t f e 30 75 gate charge (see figure 8) (v 400 vd i 4 0 ad q t e 36 80 nc (see figure 8) (v ds = 400 vdc, i d = 4.0 adc, q 1 e 7.0 e ( ds , d , v gs = 10 vdc) q 2 e 16.5 e q 3 e 12 e sourcedrain diode characteristics forward onvoltage (1) (i s = 4.0 adc, v gs = 0 vdc) (i s = 4.0 adc, v gs = 0 vdc, t j = 125 c) v sd e e 0.812 0.7 1.5 e vdc reverse recovery time (see figure 14) (i 4 0 ad v 0 vd t rr e 557 e ns (see figure 14) (i s = 4.0 adc, v gs = 0 vdc, t a e 100 e ( s , gs , di s /dt = 100 a/ m s) t b e 457 e reverse recovery stored charge q rr e 2.33 e m c internal package inductance internal drain inductance (measured from the drain lead 0.25 from package to center of die) l d e 4.5 e nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s e 7.5 e nh (1) pulse test: pulse width 300 m s, duty cycle 2%. (2) switching characteristics are independent of operating junction temperature.
3 motorola tmos power mosfet transistor device data typical electrical characteristics r ds(on) , draintosource resistance (normalized) r ds(on) , draintosource resistance (ohms) r ds(on) , draintosource resistance (ohms) v ds , draintosource voltage (volts) figure 1. onregion characteristics i d , drain current (amps) v gs , gatetosource voltage (volts) figure 2. transfer characteristics i d , drain current (amps) figure 3. onresistance versus drain current and temperature i d , drain current (amps) figure 4. onresistance versus drain current and gate voltage t j , junction temperature ( c) figure 5. onresistance variation with temperature v ds , draintosource voltage (volts) figure 6. draintosource leakage current versus voltage i dss , leakage (na) t j = 25 c 048121620 7 2 6 10 14 18 3 5 v 6 v v ds 10 v 2.0 2.8 3.6 4.4 5.2 2.4 3.2 4.0 4.8 t j = 55 c 25 c 100 c t j = 25 c v gs = 10 v 15 v 1.8 2.4 2.1 v gs = 0 v 0 200 400 1 100 10000 100 300 600 500 25 c t j = 125 c 13 7 0.6 2.2 3.8 4.6 3.0 1.4 5 t j = 100 c 25 c 55 c v gs = 10 v 50 0.2 0.6 1.0 1.8 2.2 25 0 25 50 75 100 125 150 v gs = 10 v i d = 2 a 4 v 5 1 1000 2.3 2.5 2.6 2.2 2.0 1.4 6 2 8 4 i d , drain current (amps) 5.6 24 8 6 1.9 10 800 700 0 7 3 5 1 6 2 8 4 0 13 7 5 24 8 6 100 c v gs = 10 v
4 motorola tmos power mosfet transistor device data power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are deter- mined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculat- ing rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resis- tive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate val- ues from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when cal- culating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements com- plicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a func- tion of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to mea- sure and, consequently, is not specified. the resistive switching time variation versus gate resis- tance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely op- erated into an inductive load; however, snubbing reduces switching losses. gatetosource or draintosource voltage (volts) c, capacitance (pf) figure 7a. capacitance variation figure 7b. high voltage capacitance variation v ds , draintosource voltage (volts) 10 100 1000 10000 100 10 1 c, capacitance (pf) 10 0 10152025 2800 2000 1200 400 0 v gs v ds t j = 25 c v ds = 0 v v gs = 0 v 1600 800 55 v gs = 0 v t j = 25 c 2400 1000 c oss c iss c iss c iss c rss c rss c oss c rss
5 motorola tmos power mosfet transistor device data q g , total gate charge (nc) draintosource diode characteristics v sd , sourcetodrain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 1 10 100 1000 100 10 t, time (ns) figure 8. gatetosource and draintosource voltage versus total charge v gs , gatetosource voltage (volts) v ds , draintosource voltage (volts) 01218 i d = 4 a t j = 25 c v ds v gs q1 q2 qt 36 10 6 2 0 8 4 500 400 300 100 200 v dd = 400 v i d = 4 a v gs = 10 v t j = 25 c t f t d(off) t d(on) 0.50 0.70 0.78 0 4.0 0.66 0.74 0 0.82 0.58 0.54 0.62 3.2 2.4 1.6 0.8 q3 62430 t r 3.6 2.8 2.0 1.2 0.4 v gs = 0 v t j = 25 c safe operating area the forward biased safe operating area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is for- ward biased. curves are based upon maximum peak junc- tion temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistancegener- al data and its use.o switching between the offstate and the onstate may tra- verse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power aver- aged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reli- able operation, the stored energy from circuit inductance dis- sipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a con- stant. the energy rating decreases nonlinearly with an in- crease of peak current in avalanche and peak junction temperature. although many efets can withstand the stress of drain tosource avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous cur- rent (i d ), in accordance with industry custom. the energy rat- ing must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at cur- rents below rated continuous i d can safely be assumed to equal the values indicated.
6 motorola tmos power mosfet transistor device data safe operating area figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 0 0.5 1 1.5 2.0 2.5 3 25 50 75 100 125 150 t a , ambient temperature ( c) p d , power dissipation (watts) figure 15. d 2 pak power derating curve r q ja = 50 c/w board material = 0.065 mil fr4 mounted on the minimum recommended footprint collector/drain pad size 450 mils x 350 mils 0.1 1.0 1000 100 r ds(on) limit thermal limit package limit 0.01 100 10 10 t j , starting junction temperature ( c) e as , single pulse draintosource figure 12. maximum avalanche energy versus starting junction temperature v ds , draintosource voltage (volts) figure 11. maximum rated forward biased safe operating area avalanche energy (mj) i d , drain current (amps) 0.1 t, time (s) figure 13. thermal response r(t), normalized effective transient thermal resistance r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 25 150 0 1.0e05 1.0e04 1.0e02 0.1 1.0 0.01 1.0e03 1.0e01 1.0e+00 0.2 0.1 0.05 0.02 single pulse d = 0.5 350 v gs = 20 v single pulse t c = 25 c 50 100 125 75 50 200 150 100 i d = 4 a 1.0 300 250 0.01 dc 100 m s 10 m s 1ms 10 ms 1.0e+01
7 motorola tmos power mosfet transistor device data information for using the d 2 pak surface mount package recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. mm inches 0.33 8.38 0.08 2.032 0.04 1.016 0.63 17.02 0.42 10.66 0.12 3.05 0.24 6.096 power dissipation for a surface mount device the power dissipation for a surface mount device is a function of the drain pad size. these can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . using the values provided on the data sheet, p d can be calculated as follows: p d = t j(max) t a r q ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device. for a d 2 pak device, p d is calculated as follows. p d = 150 c 25 c 50 c/w = 2.5 watts the 50 c/w for the d 2 pak package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 watts. there are other alternatives to achieving higher power dissipation from the surface mount packages. one is to increase the area of the drain pad. by increasing the area of the drain pad, the power dissipation can be increased. although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. for example, a graph of r q ja versus drain pad area is shown in figure 16. figure 16. thermal resistance versus drain pad area for the d 2 pak package (typical) 2.5 watts a, area (square inches) board material = 0.0625 g10/fr4, 2 oz copper t a = 25 c r , thermal resistance, junction to ambient ( c/w) q ja 60 70 50 40 30 20 16 14 12 10 8 6 4 2 0 3.5 watts 5 watts another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, an aluminum core board, the power dissipation can be doubled using the same footprint.
8 motorola tmos power mosfet transistor device data solder stencil guidelines prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. solder stencils are used to screen the optimum amount. these stencils are typically 0.008 inches thick and may be made of brass or stainless steel. for packages such as the sc59, sc70/sot323, sod123, sot23, sot143, sot223, so8, so14, so16, and smb/smc diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. this is not the case with the dpak and d 2 pak packages. if one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or atombstoningo may occur due to an excess of solder. for these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. the opening for the leads is still a 1:1 registration. figure 17 shows a typical stencil for the dpak and d 2 pak packages. the pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ?? ?? ?? ?? ?? ?? figure 17. typical stencil for dpak and d 2 pak packages solder paste openings stencil soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * due to shadowing and the inability to set the wave height to incorporate other surface mount components, the d 2 pak is not recommended for wave soldering.
9 motorola tmos power mosfet transistor device data typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones, and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/in- frared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177 189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 50 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies 100 c 150 c 160 c 170 c 140 c desired curve for high mass assemblies figure 18. typical solder heating profile
10 motorola tmos power mosfet transistor device data package dimensions case 418b02 issue b notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. style 2: pin 1. gate 2. drain 3. source 4. drain seating plane b s g d t m 0.13 (0.005) t 23 1 4 3 pl k j h v e c a dim min max min max millimeters inches a 0.340 0.380 8.64 9.65 b 0.380 0.405 9.65 10.29 c 0.160 0.190 4.06 4.83 d 0.020 0.035 0.51 0.89 e 0.045 0.055 1.14 1.40 g 0.100 bsc 2.54 bsc h 0.080 0.110 2.03 2.79 j 0.018 0.025 0.46 0.64 k 0.090 0.110 2.29 2.79 s 0.575 0.625 14.60 15.88 v 0.045 0.055 1.14 1.40 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 20912; phoenix, arizona 85036. 18004412447 or 6023035454 3142 tatsumi kotoku, tokyo 135, japan. 038135218315 mfax : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 mtb4n80e/d
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